1. Field of the Invention
This invention relates to semiconductor devices and in particular to intregrated circuit structures.
2. Prior Art
Numerous techniques for electrically isolating semiconductor structures have been developed and are wellknown in the art of semiconductor fabrication. See, e.g., A. H. Agajanian, "A Biography on Semiconductor Device Isolation Techniques," Solid State Technology, April, 1975. Also well-known are methods of forming oxidized isolation in integrated circuit structures. For example, U.S. Pat. No. 3,648,125 entitled "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure" issued Mar. 7, 1972, to Douglas L. Peltzer (hereinafter referred to as the Peltzer patent) discloses techniques for fabricating substantially smaller transistors, diodes, and resistors than the then existing prior art. In one such technique disclosed by the Peltzer patent, an epitaxial layer of silicon is formed on a silicon substrate and divided into electrically isolated pockets by a grid of oxidized regions of the silicon material. The oxidized regions, commonly called field regions, penetrate the epitaxial silicon to contact a laterally extending PN junction. Active and/or passive components such as diodes, transistors, and resistors may be formed in the electrically isolated pockets.
In the fabrication of vertical transistors according to the Peltzer patent and using a P type substrate and a P type epitaxial layer, a buried layer of N conductivity type semiconductor material formed in selected locations between the substrate and the epitaxial silicon layer may serve as a collector. In one embodiment, one or more emitters may then be formed by diffusion or otherwise introducing suitable impurities into the upper surface of the epitaxial silicon. The epitaxial silicon material beneath the emitter, but above the collector, functions as the base of the transistor. Ohmic contact with the buried collector regions may be achieved by any of several well-known techniques. For example, a predeposition of a desired impurity into selected regions of the expitaxial silicon followed by a diffusion of the impurity through the expitaxial silicon until the impurity contacts the buried collector can convert the selected regions of the epitaxial silicon to the same conductivity type as the buried collector, thereby providing an ohmic connection.
One problem arising in the manufacture of integrated circuits which utilize various embodiments of the oxide isolation techniques disclosed in the Peltzer patent and elsewhere is channel inversion or MOS channeling. Channel inversion may occur in oxide isolated integrated circuit structures between adjacent, but noncontiguous N type buried collector regions. Usually occurring at the interface between the P type silicon and the overlying oxide, channel inversion results from a variety of causes, for example from the presence of impurities in the oxide, typically sodium ions having a net positive charge which "mirror," or attract, electrons in the underlying P type silicon. If enough electrons are attracted, a very thin region of the P type silicon will be converted to N type semiconductor material, creating an N type channel between the adjacent buried collector regions. Channel inversion causes theoretically isolated collector regions to be effectively electrically connected to each other, thereby degrading or thwarting the function of the device and/or circuit. Channel inversion usually cannot be completely prevented by forming oxide of high purity, as only a few parts per billion of sodium impurity in the oxide may be sufficient to cause channel inversion.
Channel inversion has been studied most frequently in conjunction with the manufacture of MOS transistors in which it is necessary to prevent unwanted leakage currents and to control threshold voltages. Three of the standard MOS techniques for preventing channel inversion are: (1) channel stops (which are heavily doped regions adjacent selected surfaces), (2) other forms of surface doping control, and (3) phosphorus gettering of sodium impurities in surface oxides.
One other well known technique for preventing channel inversion is the formation of a guard ring surrounding selected regions of the integrated circuit structure. The guard ring is created by diffusing, or otherwise inserting, an impurity of a selected conductivity type into desired locations of the semiconductor material.
A further technique for preventing channel inversion has been employed by B. T. Murphy at Bell Laboratories, and is discussed in W. J. Evans et al, "Oxide Isolated Monolithic Technology and Applications," IEEE Journal of Solid-State Circuits, Vol. SC-8, No. 5, October 1973. This reference discloses that after completely forming the oxide isolation for a given device, gallium or some other material is diffused through the oxide to strongly dope (with material of opposite conductivity type to the buried collector region) those regions of semiconductor material adjacent to the oxide, thereby preventing channel inversion.